ASIC Verification Engineer

About the role

This role has been designed as ‘’Onsite’ with an expectation that you will primarily work from an HPE office.

What you'll do

• Develop and enhance ASIC verification environments using the latest methodologies such as UVM
• Architect and build block-level, subsystem, and full-chip verification environments using SystemVerilog and UVM
• Define, design, and execute verification suites and test cases for complex ASICs using front-end simulators such as VCS and NC
• Independently verify large ASIC blocks and drive tape-out readiness through code coverage, functional coverage, and gate-level simulation analysis
• Collaborate with logic designers to debug and resolve design issues, and work with software teams during bring-up and validation

What you need

• 5–9 yrs of experience
• UVM
• Verilog
• Python
• Perl
• Test cases
• B.Tech or B.E. or M.Tech

Good to have

• Shell scripting