ASIC Verification Engineer, Staff Level

About the role

ASIC Verification Engineer, Staff Level at Synopsys (incl. Ansys). Verify IP blocks and subsystems across DesignWare product lines, developing and executing verification plans, test scenarios, checkers, assertions.

What you'll do

• Verify IP blocks and subsystems across DesignWare product lines, developing and executing verification plans, test scenarios, checkers, assertions
• Build and enhance UVM-based verification environments that support block-level and subsystem-level testing, regression automation, and coverage closure
• Debug complex functional failures across IP domains like Ethernet, USB, PCI Express, or other industry-standard protocols
• Analyze regression results, track coverage metrics, and identify gaps or risks that could affect signoff quality or schedule
• Write scripts and automation utilities in Python or similar languages to improve debug efficiency, regression analysis, test development, and coverage closure

What you need

• 5–9 yrs of experience
• UVM
• Python
• Verilog
• Test cases
• Perl
• Root cause analysis
• B.Tech or B.E.