ASIC Verification- Staff Engineer

About the role

ASIC Verification- Staff Engineer at Synopsys (incl. Ansys). Specify, architect, and implement advanced verification environments for DesignWare IP cores using System Verilog and state-of-the-art methodologies.

What you'll do

• Specify, architect, and implement advanced verification environments for DesignWare IP cores using System Verilog and state-of-the-art methodologies
• Develop and execute comprehensive test plans, ensuring coverage of unit-level and system-level requirements
• Design, code, and debug testbenches, test cases, and functional coverage models to validate complex IP functionalities
• Perform functional coverage analysis and manage regression testing to achieve and maintain required quality metrics
• Collaborate closely with RTL designers and global verification teams to resolve issues and drive verification closure

What you need

• 5–9 yrs of experience
• Verilog
• Python
• UVM
• Perl
• Test cases
• Regression testing
• Any graduate