Associate II - VLSI

About the role

We are seeking a motivated SoC Design Verification Engineer to verify complex digital IPs and SoCs across various stages of the development cycle. The ideal candidate will work closely with design, architecture, and validation teams to ensure first-pass silicon success through robust verification methodologies.

What you'll do

• Develop and execute verification plans for IP and SoC-level features
• Create and enhance UVM/SystemVerilog-based verification environments
• Develop testcases, sequences, checkers, assertions, and coverage models
• Perform functional, regression, and system-level verification
• Analyze simulation results and debug RTL/design issues

What you need

• 2–5 years in electrical & electronics
• VLSI
• Verilog
• UVM
• Python
• Perl
• B.Tech or B.E.

Good to have

• FPGA
• Git
• Jenkins

What you get