Chip Top lead

About the role

We are looking for an experienced Physical Design Chip Lead to lead the end-to-end implementation of complex SoCs/ASICs. The candidate will be responsible for driving physical design activities, coordinating cross-functional teams, ensuring design closure, and meeting PPA (Power, Performance, Area) goals.

What you'll do

• Lead and own the full-chip physical design flow from RTL to GDSII
• Drive floor planning, power planning, clock tree synthesis (CTS), placement, routing, and signoff (timing, IR-drop, EM, DRC/LVS)
• Coordinate with block-level PD owners and ensure seamless integration at the chip level
• Analyse and optimize PPA to meet design targets
• Collaborate with RTL, STA, power, DFT, verification, and package teams for design convergence

What you need

• 10–18 yrs of experience
• VLSI
• Any graduate