Coherency Verification Engineer

About the role

If you're looking for an exciting opportunity to grow in a innovative environment, this could be the perfect fit for you.

What you'll do

• Verify complex digital designs at RTL level according to architecture and design specifications
• Develop and maintain verification environments using SystemVerilog and UVM
• Create, execute, and debug test plans for block-level, subsystem-level, and top-level verification
• Work on the verification of coherent systems, including cache-related functionality and interconnect behavior
• Run and manage simulations, regressions, and debug failures using industry-standard verification tools

What you need

• 8–14 yrs of experience
• UVM
• Verilog
• Python
• Perl
• Bash
• Test cases
• PhD

Good to have

• Git