Constraints Verification Applications Engineer

About the role

Constraints Verification Applications Engineer at Synopsys (incl. Ansys). Partner directly with semiconductor companies across the region to solve end-to-end constraint flow challenges including SDC generation, verification, management.

What you'll do

• Partner directly with semiconductor companies across the region to solve end-to-end constraint flow challenges including SDC generation, verification, management
• Debug constraint issues, analyze MCP (multi-cycle path), false path, and generated clock reports, and trace problems through RTL, synthesis, and timing signoff
• Build and maintain automation scripts in TCL, Perl, and Unix shell to streamline constraint generation, verification, and management workflows
• Coordinate with technical account managers and worldwide account teams to shape customer strategies, drive tool adoption, and support successful project completion
• Gather, refine, and track flow requirements based on customer feedback, engineering judgment, and emerging tool capabilities

What you need

• 5–9 yrs of experience
• VLSI
• Verilog
• Python
• Perl
• Linux
• B.Tech or B.E. or M.Tech