CPU Design Verification Engineer II

About the role

You'll verify high-performance out-of-order RISC-V CPU cores from RTL bring-up through tapeout.

What you'll do

• Own the verification plan for one or more OOO core units: extract testable features from the micro-architecture spec, define stimulus and coverage requirements
• Build and extend UVM testbench infrastructure — agents, drivers/monitors, scoreboards, reference models, functional coverage, and assertions (SVA)
• Develop constrained-random test generators and directed tests (C/assembly test programs plus SV stimulus) targeting deep pipeline states: speculative execution and…
• Debug regression failures end to end: triage waveforms, correlate RTL state against instruction-by-instruction co-simulation mismatches (PC, write-data, CSR state)
• Drive coverage closure — code, functional, and assertion coverage — including analyzing holes, adding stimulus or coverage waivers with justification

What you need

• 2–5 yrs of experience
• UVM
• Verilog
• Python
• Git
• M.Sc or B.Tech or B.E.

Good to have

• FPGA
• Prototyping