CPU Design Verification Principal Engineer

About the role

CPU Design Verification Principal Engineer at Qualcomm. Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling.

What you'll do

• Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling
• Work closely with design/verification teams within CPU to develop comprehensive test plan
• Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus
• Verify power intent through use of methodologies like UPF
• Work closely with system architects, software teams and Soc team to validate system use cases

What you need

• 8–14 yrs of experience
• C
• Verilog
• C++
• FPGA
• Test cases
• B.Sc or B.Tech or B.E. or BCA or M.Sc or M.Tech or MCA