CPU PDN & EM/IR Sign-Off Engineer (Lead/Staff)

About the role

Signal EM & Power EM Signoff for Chip TOP level & Block level CPU/DSP and other HM’s Validating the PG Grid using Grid Resistance & Secondary PG Resistance Checks Validating the IR Drops using Static IR , Dynamic IR Vless & VCD Checks for validating Die & Pkg Components of IR Drops. Python , Perl , TCL.

What you'll do

• Working with SOC and Packaging Teams on Bumps Assignments / RDL Enablement / Pkg Routing Optimizations to improve overall PDN Design
• Partnering with EDA tool vendors and internal CAD teams to develop and enhance automation flows and methodologies for improving design efficiency

What you need

• 4–10 yrs of experience
• Python
• Perl
• B.Sc or B.Tech or B.E. or BCA or M.Sc or M.Tech or MCA