CPU STA/Timing Engineer (Lead/Staff/Sr Staff)

About the role

CPU STA/Timing Engineer (Lead/Staff/Sr Staff) at Qualcomm. Work closely with CPU microarchitecture, RTL, and DFT teams to understand CPU pipelines, critical paths, and performance goals, and to define, implement.

What you'll do

• Work closely with CPU microarchitecture, RTL, and DFT teams to understand CPU pipelines, critical paths, and performance goals, and to define, implement
• Perform STA for high‑performance CPU designs at block, cluster, and SoC/top‑level hierarchies across multiple modes, corners, and scenarios
• Analyze timing on frequency‑critical CPU paths (core, cache, interconnect, clocking) and collaborate with RTL and DFT teams to drive logic and micro‑architectural fixes
• Provide actionable timing feedback to block‑level and top‑level physical design engineers to enable CPU frequency and timing closure
• Partner with CAD and methodology teams to develop, deploy, and enhance CPU‑specific timing flows and infrastructure

What you need

• 2–5 yrs of experience
• VLSI
• B.Sc or B.Tech or B.E. or BCA or M.Sc or M.Tech or MCA

Good to have

• Verilog