CPUSS Verification (Power Management), Staff/ Senior Staff

About the role

We are seeking a highly motivated and technically strong Staff Engineer to drive end-to-end verification of next-generation CPU Co-Processor (CPUCP/PDP) Power Management firmware and hardware features . This role requires deep expertise in SystemVerilog-based verification, power management validation, and cross-functional leadership across Firmware, RTL Design and Post-Silicon teams.

What you'll do

• Lead the end-to-end verification of CPUCP/PDP firmware-driven hardware features, with a focus on Power Management, Reliability, and System Readiness
• Architect and develop robust SystemVerilog/UVM testbenches, transactors, checkers, and verification infrastructure for complex SoC subsystems
• Drive verification of AMBA-based system IPs including timers, mailbox, interrupts, and interconnect fabrics (NoC)
• Own verification planning, test strategy, coverage modeling, coverage closure, and functional signoff
• Define and implement comprehensive validation for power-management features such as DVFS, Low Power Modes (LPM), clock/power transitions

What you need

• 4–7 yrs of experience
• Verilog
• UVM
• C++
• C
• Python
• Root cause analysis
• B.Sc or B.Tech or B.E. or BCA or M.Sc or M.Tech or MCA

Good to have

• CI/CD