DDR Memory Interface System Validation Lead Engineer

About the role

With more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.

What you'll do

• Own DDR5 and LPDDR5 memory subsystem validation, including defining and executing validation strategies across multiple FPGA programs
• Create, define, and develop comprehensive system-level validation environments and test suites for advanced memory interface validation
• Perform pre-silicon and post-silicon functional and electrical validation of DDR5 and LPDDR5 controllers, PHYs, and associated high-speed interfaces
• Memory initialization and training
• System margining and stress testing

What you need

• 8–14 yrs of experience
• FPGA
• Performance testing
• Root cause analysis
• B.Tech or B.E.