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Design Engineer II

Cadence·Noida

Pay not statedMid levelFull-time
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About the role

Design Engineer II at Cadence. Verification Infrastructure: Simulation testbenches in C/C++/RTL and lead the development of reusable UVM environments.

What you'll do

  • Cross-Functional Collaboration: Partner with microarchitecture, RTL design, and software teams to align verification plans with ISA requirements

What you need

  • C++
  • UVM
  • C
  • Verilog
  • Python
  • Perl
  • B.Tech or B.E. or M.Tech

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