Design Engineering Architect

About the role

This is a unique opportunity to join the HPP IP R&D Group at Cadence Design Systems. We are looking for a Sr Principal SI/PI Engineer who will be a key contributor to our advanced high speed IP products. This is a hands-on technical position.

What you'll do

• Work on test chip package design SI/PI optimization and verification
• Work on evaluation board design optimization for best SI/PI performance
• Provide extracted and measured channel models for chip designers in the R&D team
• Help with package and PCB SI/PI design guidelines and customer support on SI/PI related inquiries
• Review customer package and board designs and simulation results. Help with providing feedback to customers to ensure best possible performance of our IP in their ASIC

What you need

• 15–27 years in mechanical & production
• ANSYS
• Design systems
• PhD