Design Verification Engineer- AI Accelerator - Bangalore

About the role

We are looking for talented Design Verification Engineers to help verify and deliver Velaura's next generation Physical AI SoC. You will work closely with architects, RTL engineers, software engineers and system teams to establish confidence in the correctness, performance, reliability and safety of the design, from individual RTL blocks through complete hardware and software systems running real workloads.

What you'll do

• Work with architects to understand the intent behind a newly designed microarchitecture and turn it into detailed test and coverage plans
• Build verification environments using SystemVerilog, UVM, C and C++, with stimulus, checkers, assertions
• Develop reference models for GEMM and GEMV operations and compare hardware results against them
• Verify accelerator data flow including operand staging, tiling, accumulation and result writeback
• Verify precision, rounding and quantization behavior against the architecture specification

What you need

• C++
• C
• UVM
• Verilog
• Python
• LLMs
• B.Tech or B.E.

Good to have

• PyTorch
• Test cases