Design Verification Engineer - Bangalore

About the role

We are looking for talented Design Verification Engineers to help verify and deliver Velaura’s next-generation Physical AI SoC.

What you'll do

• Build verification environments using SystemVerilog, UVM, C/C++, assertions, formal verification, emulation, and related methodologies
• Collaborate with architects and RTL engineers to define verification plans, coverage goals, and correctness criteria
• Verify compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, and other critical SoC infrastructure
• Perform HW/SW co-verification involving firmware, drivers, runtime software, and operating system interactions
• Verify performance, latency, bandwidth, QoS, and real-time system behavior under representative workloads

What you need

• UVM
• C++
• Verilog
• C
• FPGA
• Root cause analysis
• Any graduate

Good to have

• Machine learning
• Prototyping