Design Verification Engineer

About the role

Own and execute functional verification for block‑level and full‑chip designs from specification through tape‑out Develop, execute, and maintain verification plans , test strategies, and coverage models based on design specifications Architect, develop, and maintain SystemVerilog / UVM‑based testbenches , test vectors, and assertions

What you'll do

• Own and execute functional verification for block‑level and full‑chip designs from specification through tape‑out
• Develop, execute, and maintain verification plans , test strategies, and coverage models based on design specifications
• Architect, develop, and maintain SystemVerilog / UVM‑based testbenches , test vectors, and assertions
• Run directed and constrained‑random simulations and debug functional failures to root cause
• Drive coverage closure (functional, code, and assertion coverage) and identify verification gaps

What you need

• UVM
• Verilog
• Test cases
• Any graduate