Design Verification Engineer

About the role

We are seeking a talented and detail-oriented Design Verification Engineer to join our core team. As a DV Engineer, you will play a crucial role in ensuring the functional correctness and quality of complex IP blocks and subsystems. This role requires a deep understanding of modern verification methodologies.

What you'll do

• Analyze design specifications and collaborate with architects and RTL designers to develop comprehensive, coverage-driven verification plans
• Architect, develop, and maintain robust, scalable, and reusable UVM-based testbench environments
• Implement key testbench components, including UVM agents (drivers, monitors), scoreboards, and sequences
• Develop and execute a mix of constrained-random and directed test cases to thoroughly validate design functionality and hit complex corner cases
• Debug RTL and testbench failures, performing deep root cause analysis using waveforms and logs, and work with designers to resolve issues

What you need

• 3–6 yrs of experience
• C++
• C
• UVM
• Verilog
• Python
• Test cases
• B.Tech or B.E.

Good to have

• Root cause analysis
• Perl