DFT ASIC Engineering Technical Leader | ATPG | 10 to 14 years | Bangalore

About the role

With Cisco Silicon One™, we deliver a unified, programmable silicon architecture—the foundation of all Cisco’s future routing products.

What you'll do

• Lead, mentor, and develop a team of DFT engineers responsible for designing and implementing innovative DFT features ensuring high-quality, testable
• Drive the team through the full product lifecycle, from pre-silicon design, post-silicon debug, to production qualification
• Collaborate with chip architects, design engineers, and verification teams to define, optimize, and standardize DFT strategies across multiple projects
• Supervise implementation of ATPG, scan compression, memory BIST, and other advanced DFT techniques to improve test coverage and efficiency
• Guide the debugging and root-cause analysis of silicon failures, leveraging team expertise to improve yield and reliability

What you need

• 10–14 yrs of experience
• Performance management
• Root cause analysis
• B.Tech or B.E. or M.Tech