DFT Engineer (Architect / Manager / Sr. Manager)

About the role

As a DFT Architect/Manager/Sr. Manager at Velaura AI, you will lead the definition, implementation, and execution of Design-for-Test strategies for next-generation AI and high-performance computing silicon. You will be responsible for driving test architecture, methodology, and implementation across complex ASIC/SoC designs, ensuring high test quality, manufacturability, reliability, and production readiness.

What you'll do

• Define and drive DFT architecture, strategy, and methodology for complex ASIC/SoC designs targeting AI and high-performance compute applications
• Lead the planning and implementation of DFT features including scan insertion, compression, ATPG, MBIST, LBIST, boundary scan, JTAG, IJTAG, test access
• Mechanisms, and fault simulation
• Own end-to-end DFT execution from architecture definition through RTL integration, implementation support, verification, pattern generation, sign-off, silicon bring-up
• Collaborate with architecture, RTL, verification, physical design, STA, validation, test, product engineering

What you need

• 15–27 yrs of experience
• VLSI
• Verilog
• Test cases
• B.Tech or B.E.

Good to have

• Python
• Perl