DFT Engineer ( Testchip Architecture/ RTL DFT)

About the role

We are seeking a skilled DFT Engineer to lead DFT architecture and methodology development for complex test‑chip designs. The role involves defining and implementing Scan, MBIST, ATPG, and supporting post‑silicon debug activities. The engineer will collaborate with design, verification, and physical design teams to ensure seamless BIST integration and validation.

What you'll do

• Lead the DFT architecture for test‑chip designs
• Develop and maintain DFT methodologies for the team
• Own and deliver test architectures including Scan, Mem‑BIST, ATPG, and provide post‑silicon support
• Collaborate effectively with cross‑functional design, verification, and physical design teams to ensure seamless BIST integration and validation

What you need

• 7–13 yrs of experience
• UVM
• Verilog
• Python
• VLSI
• PhD