DFT Engineer

About the role

We are seeking an experienced DFT Engineer with 5–20 years of industry experience to drive the design-for-test strategy and implementation for complex ASIC/SoC designs. The ideal candidate will have strong hands-on expertise in ATPG and Scan , with a solid understanding of test architecture, fault coverage, test pattern generation, and DFT verification.

What you'll do

• Define and implement DFT architectures for complex ASIC/SoC designs
• Develop and integrate Scan-based DFT structures across blocks and top-level designs
• Develop, run, and debug ATPG flows for stuck-at, transition, and other relevant fault models
• Analyze ATPG coverage, fault reports, pattern quality, and test compression results
• Debug ATPG failures and identify design, constraint, or test-logic issues

What you need

• 5–20 yrs of experience
• VLSI
• Python
• Perl
• Any graduate

What you get

• ₹15 L–₹80 L a year