Digital Design, Senior Engineer

About the role

Digital Design, Senior Engineer at Synopsys (incl. Ansys). Implement and own RTL for PCIe blocks and features from micro-architecture and design specs.

What you'll do

• Implement and own RTL for PCIe blocks and features from micro-architecture and design specs
• Contribute to micro-architecture discussions for your blocks; document design intent and corner cases
• Follow and help enforce RTL coding standards, lint/CDC hygiene, and review comments to closure
• Work with verification to define coverage intent, root-cause failures, and deliver fixes on schedule
• Support synthesis, timing, and low-power feedback from physical design for your blocks

What you need

• 5–9 yrs of experience
• Verilog
• VLSI
• Any graduate

Good to have

• Python
• Perl