Digital Design Verification, Staff Engineer

About the role

Digital Design Verification, Staff Engineer at Synopsys (incl. Ansys). Implement unified verification flows for Synopsys digital IP products using VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and VIPs.

What you'll do

• Build scalable verification infrastructure from the ground up, designing environments that support complex IP and SoC projects across global teams
• Lead and mentor verification engineers, providing technical guidance on UVM, SystemVerilog, flow optimization, and debugging strategies
• Drive technical initiatives independently, managing high-impact assignments from concept through deployment and adoption
• Collaborate with EDA tool development teams to influence product roadmaps, provide feedback, and optimize verification workflows for real-world use cases
• Troubleshoot and refine verification processes for internal teams and customers, diagnosing flow bottlenecks and delivering solutions that stick

What you need

• 4–7 yrs of experience
• UVM
• Verilog
• Python
• B.Tech or B.E.