Director, SoC Design Verification and Virtual Platform Quality

About the role

This role offers the opportunity to shape a differentiated verification strategy at the intersection of semiconductor Design Verification, SystemC modeling, Virtual Platforms, and pre-silicon software development . This leader will define and execute a reuse-first verification strategy spanning SystemC transaction-level models, RTL, IP, subsystem, SoC, and platform-level validation .

What you'll do

• Define and drive the verification strategy for SystemC models, RTL designs, reusable IP, subsystems, SoCs, and Virtual Platforms
• Lead and develop a global Design Verification organization, including verification leads, engineers, external partners, and project-specific teams
• Establish a common verification architecture that supports reuse of test intent, stimulus, sequences, checkers, scoreboards, assertions, coverage models
• Develop scalable SystemVerilog/UVM environments , including protocol adapters and TLM bridges that connect pin-level UVM interfaces to SystemC/TLM models
• Establish functional-equivalence and timing-correlation methodologies between SystemC LT/AT models and RTL implementations

What you need

• 15–27 yrs of experience
• UVM
• Verilog
• CI/CD
• C++
• Python
• Root cause analysis
• B.Tech or B.E.

Good to have

• FPGA
• Prototyping