DTMA & Memory Controller Design Lead

About the role

The DTMA & Memory Controller Design Lead owns the Data Transfer and Memory Access (DTMA) engine together with HBM4e memory-controller integration. You will orchestrate all data movement between the 512-bank SRAM (8 TB/s), the 6-stack HBM4e subsystem (384 GB, 12 TB/s), and the PE arrays — the subsystem that keeps xPU's compute engine saturated.

What you'll do

• Own micro-architecture and RTL of the DTMA engine managing data movement between SRAM banks, HBM4e, and the BFOS PE arrays
• Define the compute-to-memory interface with the DTMA engine and SRAM banks to keep PE arrays fully fed at bandwidth
• Lead integration and configuration of HBM4e memory controllers across 6 stacks (384 GB, 12 TB/s aggregate)
• Design descriptor-based DMA, gather/scatter, tensor-tiling, and prefetch mechanisms optimized for BFOS dataflow
• Architect the 512-bank, 8 TB/s SRAM access scheduling, bank arbitration, and conflict-avoidance logic

What you need

• 10–18 yrs of experience
• Machine learning
• System design
• C++
• Arbitration
• Verilog
• C
• M.Tech or M.Sc or B.Tech or B.E.

Good to have

• Python