DV Lead Engineer

About the role

We are seeking a highly skilled and meticulous Gate-Level Simulation (GLS) Verification Engineer to serve as the last line of defense before silicon tape-out . In this critical role, you will be responsible for verifying the post-synthesis, final netlist of our complex SoCs, ensuring that the design's functionality remains correct after synthesis, placement, and routing.

What you'll do

• Own and execute the complete GLS verification strategy for complex IPs and full-chip SoCs, from initial planning to final sign-off
• Bring up, maintain, and debug existing UVM/SystemVerilog testbenches in both zero-delay and back-annotated ( SDF ) timing simulation environments
• Timing-dependent race conditions and glitches
• Reset propagation and synchronization issues
• X-propagation bugs masked by optimistic RTL simulation

What you need

• 8–14 yrs of experience
• Perl
• Python
• Verilog
• UVM
• VLSI
• B.Tech or B.E.