Engineer-std cell layout

About the role

Responsible for on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment. Guide junior team-members in their execution of Sub block-level layouts & review their work.

What you'll do

• Design and maintain standard cells layout for new DRAM products on new technology
• Perform layout verification like LVS/DRC/Latchup, quality check and documentation
• Responsible for on-time delivery of block-level layouts with acceptable quality
• Guide junior team-members in their execution of Sub block-level layouts & review their work
• Contribute to effective project-management

What you need

• Any graduate