FCT PD lead

About the role

As an FCT Lead within the Physical Design organisation, you will lead Full Chip Timing (FCT) execution and timing signoff activities for complex SoC and subsystem designs. You will work closely with Architecture, Design, PD, STA, DFT, CAD and Methodology teams to achieve first-pass silicon success and deliver timing closure for industry-leading products THE PERSON: A successful candidate will work with senior silicon design engineers.

What you'll do

• Lead Full Chip Timing (FCT) execution and timing signoff activities for complex SoC and subsystem designs
• Responsible for timing constraints development and timing signoff
• Own end-to-end timing closure and signoff for SoC and subsystem integration projects
• Define, develop and validate SDC constraints, clocks and timing methodologies
• Drive timing convergence across synthesis, P&R, CTS, route and post-route ECO stages

What you need

• 14–25 yrs of experience
• VLSI
• Python
• Perl
• B.Tech or B.E. or M.Tech