Firmware Architect

About the role

Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.

What you'll do

• Define firmware architecture for 224G/lane AEC retimer (boot, config, calibration, link training, equalization, FEC, telemetry)
• Implement link training for IEEE 802.3ck (100G/lane) and 802.3dj (200G/lane), including adaptation algorithms and fallbacks
• Own FEC interaction (KP4, RS-544) and telemetry pipeline for Predictive Telemetry
• Lead silicon bring-up, partnering with ASIC design and signal integrity
• Ensure standards compliance (IEEE 802.3ck/dj, OIF-CEI, CMIS, OSFP)

What you need

• 8–10 yrs of experience
• Embedded C
• C
• Python
• CI/CD
• VLSI
• Calibration
• CMA or B.Sc or B.Tech or B.E.