Formal Verification Engineer

About the role

We are looking for a skilled Formal Verification Engineer to join our SoC verification team and ensure the correctness, robustness, and reliability of complex digital hardware designs using advanced formal verification methodologies. In this role, you will collaborate closely with RTL designers, design verification engineers, and architects to validate critical SoC components throughout the development lifecycle.

What you'll do

• Develop, maintain, and execute formal property checks, including assertions, assumptions, and coverage, for complex SoC components such as interconnects
• Perform block-level and chip-level formal verification using industry-standard formal verification tools
• Collaborate with RTL and design verification teams to debug counterexamples, resolve design issues, and achieve formal verification closure
• Define and enhance formal verification methodologies, reusable verification frameworks, and best practices across projects
• Contribute to verification planning, coverage analysis, closure tracking, and tape-out sign-off activities

What you need

• 3–8 yrs of experience
• Verilog
• VLSI
• Root cause analysis
• B.Tech or B.E.

Good to have

• Python
• Perl

What you get

• ₹5 L–₹22 L a year