Full-Chip STA Signoff Engineer

About the role

We are looking for an experienced Full-Chip STA Signoff Engineer with 6–17 years of hands-on experience in Static Timing Analysis and timing closure for complex SoC designs. The ideal candidate will have strong expertise in full-chip STA signoff , timing analysis, constraint development, timing closure, and signoff methodologies across advanced semiconductor process nodes.

What you'll do

• Own and execute full-chip Static Timing Analysis (STA) signoff for complex SoC designs
• Perform timing analysis across multiple modes and corners (MMMC) and ensure complete timing coverage
• Analyze setup, hold, recovery, removal, minimum pulse width, clock gating, and other timing checks
• Develop, review, and maintain timing constraints including SDC, clocks, generated clocks, input/output delays, false paths, multicycle paths, and clock uncertainty
• Debug and resolve timing violations across functional and test modes

What you need

• 6–17 yrs of experience
• VLSI
• Python
• Perl
• B.Tech or B.E. or M.Tech

What you get

• ₹14 L–₹32 L a year