Full Chip Timing Lead

About the role

MTS Full chip STA (FCT) SILICON DESIGN ENGINEER THE ROLE: As a member of the PD Full Chip STA closure and optimization team, you will work on SoC Full Chip Timing closure which includes high frequency CPU, HBM, DDR, Serdes interfaces. You will be responsible for SDC validation and timing signoff execution with different team members and will work closely with the methodology and CAD teams across various geographies to achieve first pass silicon success.

What you'll do

• Work on SoC Full Chip Timing closure which includes high frequency CPU, HBM, DDR, Serdes interfaces
• Be responsible for SDC validation and timing signoff execution with different team members and will work closely with the methodology and CAD teams across various…
• Drive team towards common requirements and flows Experienced in deploying and implementing ML techniques and algorithms in physical design

What you need

• 7–13 yrs of experience
• VLSI
• Python
• Verilog
• Machine learning
• Dashboarding
• Perl
• Any graduate