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HIring for ASIC verification

Happiest Minds Technologies·Bengaluru

Pay not stated5–8 yrsFull-time
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About the role

Implement verification environment independently using high level verification languages like System Verilog Understand and execute the existing verification flows and improve the framework Contribute to verification methodology development and implementation

What you'll do

  • Implement verification environment independently using high level verification languages like System Verilog
  • Contribute to verification methodology development and implementation

What you need

  • 5–8 yrs of experience
  • UVM
  • Verilog
  • B.Tech or B.E. or M.Tech

Good to have

  • FPGA

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