IP Logic Design Engineer

About the role

This role spans architecture, Verilog/SystemVerilog implementation, Quartus flows and timing closure, board bring-up, interface validation, and system-level debug. The ideal candidate can move comfortably from a system requirement or board schematic to a robust RTL implementation, then bring the design up on hardware and isolate issues across RTL, board, clocking, reset, memory, transceiver, and software boundaries.

What you'll do

• Define FPGA architecture, microarchitecture, block diagrams, interface behavior, register maps, clocking, reset strategy
• Design, RTL code, integrate, and maintain reusable synthesizable RTL using Verilog and SystemVerilog
• Translate board and system requirements into RTL features, diagnostics, loopback paths, manufacturing-test functions, and example designs
• Support board bring-up from first power-on through FPGA configuration, clock and reset validation, memory initialization, interface enablement
• Work on one or more of the following interface areas: PCIe, Ethernet, DDR/EMIF, high-speed serial transceivers, FMC, QSFP, USB, UART, I2C, SPI, GPIO

What you need

• 10–18 yrs of experience
• FPGA
• Verilog
• VLSI
• Performance testing
• B.Tech or B.E.

Good to have

• Python
• Linux