Layout Design, Sr Staff Engineer

About the role

Layout Design, Sr Staff Engineer at Synopsys (incl. Ansys). Lead complete physical layout development for advanced memory IP including SRAM, ROM, eDRAM, and emerging memory types across nodes from 3nm to mature technologies.

What you'll do

• Lead complete physical layout development for advanced memory IP including SRAM, ROM, eDRAM, and emerging memory types across nodes from 3nm to mature technologies
• Drive layout architecture decisions at every level: bit-cell topology, array organization, peripheral circuits, power distribution, and full memory integration
• Define and implement layout methodologies that improve area efficiency, performance, power consumption, and manufacturability while meeting aggressive yield targets
• Resolve complex DRC, LVS, ERC, and EMIR issues in dense memory structures
• Lead RC extraction, parasitic analysis, and signal integrity optimization efforts, collaborating with circuit designers to close timing, power

What you need

• 10–18 yrs of experience
• Physics
• Power systems
• B.Tech or B.E. or M.Tech