Layout Design, Sr Staff Engineer

About the role

Layout Design, Sr Staff Engineer at Synopsys (incl. Ansys). Lead layout development for next generation DDR and HBM PHY IP across 7nm, 5nm, 3nm, and future nodes using FinFET and GAA process technologies.

What you'll do

• Lead layout development for next generation DDR and HBM PHY IP across 7nm, 5nm, 3nm, and future nodes using FinFET and GAA process technologies
• Drive floorplanning, layout matching, ESD hardening, latch-up mitigation, and PERC/EMIR closure for analog and mixed-signal blocks in high-speed memory interfaces
• Own effort estimation, schedule planning, and execution for layout projects, coordinating across design, verification, and customer engagement teams
• Mentor junior layout engineers on deep submicron effects, DFM best practices
• Conduct layout reviews, manage quality checks using Calibre and internal flows, and drive LEF generation, bond-pad layout, IO frame design, and release processes

What you need

• 8–14 yrs of experience
• B.Tech or B.E. or M.Tech