Lead Design Engineer

About the role

Lead the design and integration of complex SoC, subsystem, and IP blocks from architecture interpretation through RTL delivery and design closure. Own micro-architecture, RTL development, quality reviews, and cross-functional coordination with verification, physical design, DFT, firmware, and architecture teams.

What you'll do

• Own end-to-end RTL design and development of SoC, subsystem, and IP blocks
• Translate architecture and product requirements into detailed micro-architecture and implementation plans
• Develop high-quality RTL in Verilog/SystemVerilog with focus on correctness, reusability, and scalability
• Lead design of key blocks such as interconnects, controllers, bridges, memory interfaces, datapaths, and control logic
• Drive block-level and subsystem-level design integration and resolve interface, timing, and functionality issues

What you need

• 10–14 yrs of experience
• Verilog
• Python
• Arbitration
• Perl
• VLSI
• Test cases
• B.Tech or B.E. or M.Tech