Lead Design Engineer

About the role

Manage regression infrastructure that tracks quality of the RTL/flow development as well as the PPA of the key designs. Digital design implementation using Cadence EDA tools - Genus, Innovus, Conformal, Litmus, Tempus, Voltus, Certus, Pegasus and other backend tools Candidate will be working on automation of Full chip floorplanning using latest AI tools.

What you'll do

• Develop TFM to optimize PPA for IP’s and Soft Controllers
• Manage regression infrastructure that tracks quality of the RTL/flow development as well as the PPA of the key designs

What you need

• 5–9 yrs of experience
• VLSI
• Python
• Maintenance
• B.Tech or B.E. or M.Tech or M.Sc