Lead Design Engineer ( Synthesis/LEC/CLP )

About the role

We are looking for a Lead Design Engineer to provide hands-on execution across Synthesis, LEC, CLP, and UPF/power-intent flows for advanced ASIC/SoC designs. This role is execution-focused with growing ownership: debugging synthesis and LEC issues independently, contributing to CLP sign-off, and writing constraints and ECO scripts, while working closely with the Team on complex escalations.

What you'll do

• Run and debug LEC sign off on design blocks; investigate and resolve NEQs and constraint mismatches
• Work on Genus synthesis runs to improve QoR, debug SDC/constraint issues
• Write and maintain ECO scripts and timing/power constraints for design blocks
• Independently triage and document issues, escalating complex or systemic issues as needed
• Collaborate with PD, DFT, and RTL teams to resolve cross-functional issues affecting synthesis/LEC/CLP closure

What you need

• 5–8 yrs of experience
• Python
• Linux
• Perl
• System design
• Customer success
• Learning and development
• B.Tech or B.E. or M.Tech or M.Sc