Lead DFT Engineer - MBIST

About the role

We are seeking an experienced Design-for-Test (DFT) Engineer at the Senior Member of Technical Staff (SMTS) level with over 10 years of industry experience. The candidate will be responsible for architecting, implementing, and validating advanced DFT solutions across complex SoCs. The role requires strong expertise in MBIST, SCAN Insertion, ATPG and simulation (RTL & GLS) , and close collaboration with PnR teams to ensure testability and design closure.

What you'll do

• Define and implement DFT architecture including Scan, MBIST, and Test Access Mechanisms
• Lead Scan Insertion , ATPG Pattern Generation
• Develop and integrate MBIST solutions for embedded memories (SRAM/MRAM/ROM)
• Perform RTL-level DFT verification and debug
• Execute and debug Gate-Level Simulations (GLS) with SDF back-annotation

What you need

• 10–18 yrs of experience
• UVM
• Verilog
• Python
• VLSI
• Any graduate