Lead digital verification engineer

About the role

We are seeking a Lead Digital Verification Engineer to join NXP’s NVM IP design group in Bangalore, India. This role involves leading and managing verification activities for a diverse NVM IP portfolio of L-NVM, RRAM and MRAM, developing and maintaining verification flow and environment, and collaborating with NXP product design teams to deliver high-quality, scalable NVM IP solutions across multiple business verticals.

What you'll do

• Responsible for the pre-silicon verification of non-volatile memory controller modules
• Responsible for defining digital verification strategy and plan for IP modules
• Interface to Digital design teams to understand functionality and application of the IP subsystem, SoC system
• Responsible for executing verification plan according to the product specification and verification requirements defined
• Responsible for developing, debugging and running System Verilog UVM based verification environment for RTL/netlist simulation

What you need

• 8–14 yrs of experience
• Verilog
• UVM
• Test cases
• B.Tech or B.E.

Good to have

• Python
• Perl