Lead Emulation Engineer

About the role

This is a greenfield role and the first emulation hire at the company. There is no existing flow to inherit and no one above you who has done this here before. You will define how emulation works at Anthriq, hold the standard that keeps RTL emulation-ready, and build a team who will run the platform with you.

What you'll do

• Drive installation through to first successful full-chip compile
• Own the compile flow end to end partitioning, capacity allocation, compile turnaround time, and incremental compile strategy
• Own capacity planning and platform roadmap
• Define and enforce the emulation-readiness standard for RTL: clock and reset structure, gated clocks, memory inference and mapping, initialization and X-handling
• Work directly with the design team so RTL arrives emulation-clean

What you need

• 8–12 yrs of experience
• Python
• Verilog
• UVM
• FPGA
• Prototyping
• Any graduate