Lead Engineer – CAD Digital Verification

About the role

In this role, you will develop, enhance, and support CAD tools and EDA simulation flows that enable efficient and reliable verification of Silicon Labs' semiconductor products. You will work on automation, simulation methodologies, and verification infrastructure to improve engineering productivity, design quality, and overall development efficiency.

What you'll do

• Develop, deploy, and maintain CAD tools and EDA flows supporting Design Verification, Formal Verification, Low Power, Functional Safety, and Coverage Analysis
• Work closely with RTL design and verification teams to understand technical requirements, identify challenges, and develop solutions that improve engineering productivity
• Develop and optimize automation scripts using Python, Perl, Tcl, Bash, and shell scripting to streamline simulation builds, testbench generation
• Support ASIC/SoC simulation environments, including RTL simulation, gate-level simulation (GLS), and UVM-based verification flows
• Collaborate with EDA vendors such as Cadence, Synopsys, and Siemens EDA to integrate new capabilities, debug tool issues, and resolve simulation bottlenecks

What you need

• 7–13 yrs of experience
• Verilog
• Shell scripting
• UVM
• C++
• Python
• Perl
• B.Tech or B.E.

Good to have

• C
• Linux
• Bash