Lead FPGA Timing & Characterization Silicon Design Engineer

About the role

Lead FPGA Timing & Characterization Silicon Design Engineer We are seeking a highly motivated and experienced Senior Member of Technical Staff (SMTS) to lead the development, validation, silicon correlation, and release of FPGA timing models.

What you'll do

• Establish comprehensive validation frameworks for FPGA timing library quality assessment
• Drive root-cause analysis for timing discrepancies and model inaccuracies
• Develop and maintain regression suites, DRC checks, and release signoff criteria
• Drive characterization of FPGA resources Develop automation flows to improve FPGA timing quality Own planning and execution of Timing Library releases aligned with…
• Perform QoR analysis on Vivado software and compare timing results across releases, speed grades, and device generations

What you need

• 10–18 yrs of experience
• FPGA
• VLSI
• Python
• Root cause analysis
• Perl
• M.Tech or M.Sc