Lead Full-chip STA and timing signoff Engineer

About the role

We are seeking an experienced Full Chip SoC Timing Lead in ASIC/SoC design implementation and timing closure. The ideal candidate will lead full-chip timing activities from synthesis through place-and-route, signoff, and tapeout for complex SoCs in advanced technology nodes.

What you'll do

• Own and drive timing signoff from synthesis to final tapeout
• Develop, validate, and maintain timing constraints including SDC for full-chip and block-level integration
• Perform and review static timing analysis (STA) for setup, hold, recovery, removal, clock gating, and async paths
• Drive MMMC timing methodology and ensure robust timing convergence across PVT corners
• Work closely with physical design teams on floorplanning, placement, CTS, routing, and post-route timing optimization

What you need

• 12–22 yrs of experience
• VLSI
• Verilog
• B.Tech or B.E.