Lead PERC Rule Deck Development Engineer

About the role

The Lead PERC Rule Developer will drive PERC methodology , rule development, and flow enablement for ESD, latch-up, power-domain, connectivity, and reliability-related verification. The role requires strong hands-on expertise in Calibre LVS/PERC, CMOS and FinFET fundamentals, analog/mixed-signal design flows, and close collaboration with cross-functional design, CAD, technology, and verification teams across multiple sites and time zones.

What you'll do

• Lead development, enhancement, validation, and release of Calibre PERC rule decks for ESD, latch-up, power-domain, connectivity, and reliability verification requirements
• Translate technology, product, and design signoff requirements into scalable, maintainable PERC checks and reusable verification methodologies
• Drive PERC flow enablement across IP, block, subsystem, and SoC design stages, ensuring consistent integration with LVS, extraction
• Debug complex PERC/LVS issues in collaboration with design, layout, CAD, and technology teams; provide clear root-cause analysis and actionable closure recommendations
• Develop automation scripts, regression suites, quality checks, and reporting utilities to improve rule development efficiency, release quality, and traceability

What you need

• 10–18 yrs of experience
• Python
• VLSI
• Perl
• Root cause analysis
• Test cases
• B.Tech or B.E. or M.Tech