Lead Principal Engineer Design

About the role

Responsible for leading Physical Design and Timing Closure of lowpower SoCs targeted for IoT/MCU markets. - Responsible to achieve die area, performance, power goals forhierarchical blocks and top. Drive physical design implementation which includes package co-design,floorplanning, power grid design and signoff, place and route, timingclosure, physical verification checks. - Influence tools, flows and methodology activities to improve upon QoR.

What you'll do

• Have the opportunity to merge creativity with your
• Responsible for leading Physical Design and Timing Closure of lowpower SoCs targeted for IoT/MCU markets. -
• Responsible to achieve die area, performance, power goals forhierarchical blocks and top
• Drive physical design implementation which includes package co-design,floorplanning, power grid design and signoff, place and route, timingclosure
• Interact with cross-functional team members to improve design,methodology and process aspects

What you need

• VLSI
• Customer success
• IoT
• Any graduate