Lead Principal Engineer, Design Verification

About the role

Lead and manage a Design Verification team , ensuring delivery of verification achievements and project commitments Define and drive verification strategy, architecture, and coverage goals for complex designs and programs Own verification planning, execution, reviews, and sign‑off , including functional, timing, and mixed‑signal verification

What you'll do

• Lead and manage a Design Verification team , ensuring delivery of verification achievements and project commitments
• Define and drive verification strategy, architecture, and coverage goals for complex designs and programs
• Own verification planning, execution, reviews, and sign‑off , including functional, timing, and mixed‑signal verification
• Collaborate with Design Engineering to understand specifications, circuit intent, and performance metrics for design
• Partner with multi-functional teams (Product Engineering, Technology Development, CAD, Validation) to ensure alignment and issue resolution

What you need

• 8–16 yrs of experience
• Circuit design
• Verilog
• UVM
• Performance management
• B.Tech or B.E.